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SUMMIT
MICROELECTRONICS, Inc. 8-Channel Auto-MonitorTM ADC In System Programmable Analog (ISPATM) Device
FEATURES
! Programmable 8 Channel 10-Bit A to D con-
SMD1108
Preliminary
! Programmable LED Driver Outputs ! Programmable, Nonvolatile Combinatorial Reset
verter " Programmable Sequencing of Analog Switches in Auto-Monitor Mode " Resolution of 10 bits " Differential Non-Linearity of 1LSB " Top 4 Channels Programmable, Nonvolatile Upper/Lower IRQ Limits " Bottom 4 Channels Tied to Matching Programmable, Nonvolatile Comparators " 4 Companion Over-current Comparators
! Internal Temperature Sensor
logic
! Nonvolatile Status Capture Register ! Two Programmable, Nonvolatile Watchdog
Timers
! 1K-Bit Nonvolatile Memory ! Industry Standard 2-Wire Interface
" Nonvolatile Configuration Registers " ADC Conversion Results " Memory Array " Mechanism for System Level Presence Detect
SIMPLIFIED APPLICATION DRAWING
5V I2C 5V
VCC0/CH4
OC0
CURRENT SENSOR
CH1
VCC1/CH5 OC1 LDO VCC2/CH6 OC2 2.5V
SMD1108
AIRFLOW SENSOR ENVIRONMENTAL MONITOR CH2
CH3
Internal Temp. Sensor
OC0
EXT. TEMP. SENSOR
CH0
LDO
3.3V
LDO VCC3/CH7 OC3
1.8V
AUXVCC
SMBALERT
RDY#
RST#
RESET#
2052 SAD
(c)SUMMIT MICROELECTRONICS, Inc., 2001 * 300 Orchard City Dr., Suite 131 * Campbell, CA 95008 * Phone 408-378-6461 * FAX 408-378-6586 * www.summitmicro.com Characteristics subject to change without notice 2052 2.0 10/05/01
1
SMD1108
Preliminary
FUNCTIONAL BLOCK DIAGRAM
WD_EN# WLDI 3 VCC 48 WDO# 2 LDO# IRQ_RST# 1 7 OC_IRQ# 12 OV_IRQ# 13
All Resistors are 100k
DLYD_RST# 14 RST# 15 MR# 5 AUTOMON 9 LIM_IRQ# 11 SMBALERT 4 Hi Lo Hi Lo Hi Lo Hi Lo 00112233 Programmable Combinatorial Logic 23 HEALTHY# 16 UV_OVRD
Nonvolatile Programmable Combinatorial Reset Logic Reset Timer
U
Nonvolatile Programmable Watchdog Timer Logic
U
24 FAULT# Programmable Combinatorial Interrupt Logic Nonvolatile Status Register
U
10 FAULT_IRQ#
VREFIN 29
-O -O NV -O NV -O
VREFOUT 20 RDY# 6 10-Bit ADC Reference Select & Trim Logic
NV
NV
U
+
+
+
+
+
+
+
+
50 mV
-
-
-
-
-
50 mV
50 mV
-
50 mV
-
-
AUXVCC 42 Memory Array GPO-0 28 GPO-1 27 GPO-2 26 GPO-3 25 A0 43 A1 44 A2 45 SDA 46 SCL 47 CE# 22 Temperature Sensor
41 VCC0/CH4 40 VCC1/CH5 39 VCC2/CH6 38 VCC3/CH7 34 OC3
Serial Interface
Four General Purpose Outputs
Programmable Octal Analog Switch
35 OC2 36 OC1 37 OC0
Power Control & Distribution
All Resistors are 100k
VCC 33 32 31 30 19 AGND
21
17
18
8 GND
2052 BD 1.1
CH0 CH1 CH2 CH3
Reserved
PGND DGND
RECOMMENDED OPERATING CONDITIONS Temperature Voltage -40C to 85C. 2.7V to 5.5V
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SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
INTRODUCTION
The SMD1108 is a versatile, programmable 8-channel, 10-bit Data Acquisition System that is designed to operate autonomously, relieving the system host and logic board of the environmental monitoring tasks. Programming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from Summit Microelectronics.
PIN CONFIGURATION
48-Pin TQFP
48 47 46 45 44 43 42 41 40 39 38 37
WLDI SCL SDA A2 A1 A0 AUXVCC VCC0/CH4 VCC1/CH5 VCC2/CH6 VCC3/CH7 OC0
LDO# WDO# WD_EN# SMBALERT MR# RDY# IRQ_RST# GND AUTOMON FAULT_IRQ# LIM_IRQ# OC_IRQ#
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
OC1 OC2 OC3 CH0 CH1 CH2 CH3 VREFIN GPO-0 GPO-1 GPO-2 GPO-3
OV_IRQ# DLYD_RST# RST# UV_OVRD PGND DGND AGND VREFOUT Reserved CE# HEALTHY# FAUALT#
13 14 15 16 17 18 19 20 21 22 23 24
2052 PCon 1.0
SUMMIT MICROELECTRONICS, Inc.
2052 2.0 10/05/01
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SMD1108
Preliminary
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ...................... -55C to 125C Storage Temperature ........................... -65C to 150C Lead Solder Temperature (10s) ......................... 300 C Output Short Circuit Current ........................ # 100mA Terminal Voltage with Respect to GND (AGND, DGND & PGND tied): Digital Inputs:IRQ_RST#, WD_EN#, MR#, WLDI, SCL, CE#, A0, A1, A2, and AUTOMON .... -2V to 7V Digital Outputs: ................. LDO#, WDO#, SMBALERT#, HEALTHY#, FAULT_IRQ#, LIM_IRQ#, OC_IRQ#, RST#, OV_IRQ#, DLYD_RST#, FAULT#, RDY#, GPO-0, GPO-1, GPO-2, and GPO-3 ............................................. -2V to 7V Analog Inputs: VCC0/CH4, VCC1/CH5, VCC2/CH6, VCC3/CH7, CH0, CH1, CH2, CH3, OC1, OC2, OC3, AUXVCC, and VREFIN .............. -2V to 7V # Output shorted for no more than one second, no more than one output shorted at a time.
DC OPERATING CHARACTERISTICS
(Over Recommended Operating Conditions; Voltages are relative to GND) Symbol ICC ISB ILI ILO VOL1 VOL2 VOH VIL VIH VREFIN VIN1 VIN2 VIN3 IVRO Parameter Supply Current Standby Current Input leakage current Output leakage current Output low voltage Conditions (Note 1) All outputs open All outputs open, ADC idle, no memory in process VIN = 0V to VCC VOUT = 0V to VCC IOL = 5mA IOL = 1mA VCC = 5V, IOL = 2.1mA VCC < 4.5V, IOL = 1mA VCC = 5V, IOL = -400mA VCC < 4.5V, IOL = -100mA 2.4 VCC - 0.2 -0.1 2 0.3 x VCC VCC + 1 5 5.5 2 x VREFIN VCC 1 1 Min. 1 0.1 Typ. Max. 3 1 2 10 0.4 0.4 0.4 0.2 Units mA mA A A V
Output low voltage
V
Output high voltage Input low voltage Input high voltage
V V V
Analog Inputs VREF input voltage Input voltage on VCC0/CH0 through VCC3/CH3 Input voltage on channels 4 through 7 Input voltage on OC0 through OC3 VREFOUT current VREFOUT = 2.5V VREFOUT = 2.048V 1 0 0 0 V V V V mA
2052 Elect Table 1.0
Note 1: Unless otherwise specified VCC is the highest of the four VCCX/CHX inputs.
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SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
PIN DESCRIPTIONS
VCC0/CH4 - VCC3/CH7 (38, 39, 40, 41) These 4 inputs are used as the voltage monitor inputs and the voltage supply for the SMD1108. Internally they are diode ORed and the input with the highest voltage potential will be the default supply voltage. For proper device operation at least one of the inputs must be at 2.7V or higher. VCC0/CH4 to VCC3/CH7 are also inputs to four programmable comparators. The under-voltage and over-voltage threshold voltage of each comparator is programmable. VREFIN (29) A reference voltage for the ADC. The user can select either the VREFIN as the ADC reference or use the default internal reference voltage. VREFOUT (20) The internally generated reference voltage. It is programmable and can supply either 2.048V or 2.500V. AGND, DGND, PGND, GND (19, 18, 17, 8) These are the analog, digital, package, and common ground inputs, respectively. They should all be tied to the same ground plane. AUXVCC (42) AUXVCC should be isolated from the system power supplies and tied to ground through capacitor CB/U. During normal device operation CB/U will be charged by the system supplies through the SMD1108. If system power is lost the charge on CB/U will be used to store the status of the monitor inputs. A 10F tantalum capacitor should be used for CB/U. In the system environment AUXVcc could also be connected to the front of the card (along with SDA and SCL and GND) so that power could be applied to the SMD1108 to read the contents of the NV status registers. A0, A1 and A2 (43, 44, 45) Address inputs. When addressing the SMD1108 either as a memory or an analog channel (or configuration register) the address inputs distinguish which one of eight possible devices sharing the common bus is being addressed. CE# (22) A control mechanism for the 2-wire interface. The true state polarity is programmable. When driven true the interface is active and communications channels are open. When it is driven false all communications via the bus are disabled.
SUMMIT MICROELECTRONICS, Inc.
SDA (46) Serial data input/output pin. It should be tied to VCC through a 10k pull-up resistor. SCL (47) Serial clock input pin. It should be tied to VCC through a 10k pull-up resistor. CH0 to CH3 (33, 32, 31, 30) The analog channel inputs. These inputs are monitored solely through the use of the ADC. OC0 to OC3 (37, 36, 35, 34) Over-current sense inputs. They are paired with VCC0/ CH4 to VCC3/CH7, respectively, and have a fixed 50mV offset with respect to their corresponding channel input. MR# (5) An active low manual reset input. When MR# is driven low the reset output will immediately be driven low. MR# is not maskable and will always generate a reset sequence. The duration of the RST# pulse will be equal to the length of the MR# input pulse plus the programmed reset time-out period value. WD_EN# (3) The enable input for both the Watchdog and the Longdog. It must be driven low to enable the operation of their timers. This can provide a convenient mechanism during "debug of code" or during a "power-on configuration" sequence. WLDI (48) The Watchdog timer interrupt input. A low to high transition on WDI will reset the Watchdog and Longdog timers. If the timer is not reset within the programmed period of time the SMD1108 will activate the WDO# output first and then the LDO# output. RST# (15) An active low open drain output. It will be driven low by the combination of VCC0/CH4 to VCC3/CH7 being at levels below their programmed settings and/or MR# being driven low. RST# will stay low for the duration of the fault condition or the MR# low input and remain low for the duration of tPURST after the removal of the fault condition or MR# returning high.
2052 2.0 10/05/01
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SMD1108
Preliminary
DLYD_RESET# (14) An active low open drain output. During normal system operation it will be driven low by the combination of VCC0/ CH4 to VCC3/CH7 being at levels below their programmed settings. During the power-on sequence it will be delayed to allow the system to power-up in a controlled sequenced order. See Table 19 for the delay values. SMBALERT# (4) An active low open drain output. It will be driven low whenever one or more of the four auto-monitor inputs exceeds its limits. Once the SMBALERT# output is driven low the SMD1108 will respond to the industry standard SMB protocol and identify itself as the generator of the alert. LIM_IRQ# (11) An active low open drain output that is programmable to be driven low whenever any one of the selected auto-monitor inputs exceeds the programmed high or low value. FAULT# (24) An open drain output that can be programmed to drive the output low whenever a selected source is out of limits (FAULT#). Conversely it can be programmed to drive the output low (FAULT) whenever the selected sources are within limits. HEALTHY# (23) An open drain output that can be programmed to drive the output low whenever a selected source is out of limits (HEALTHY). Conversely it can be programmed to drive the output low whenever the selected sources are within limits (HEALTHY#). WDO# (2) Watchdog Timer Output is an active low open drain output that can be wire-ORed with any number of open drain outputs. Whenever the programmed time-out period of the Watchdog timer is exceeded this output will be driven low. LDO# (1) Longdog Timer Output is an active low open drain output that can be wire-ORed with any number of open drain outputs. Whenever the programmed time-out period of the Longdog timer is exceeded this output will be driven low.
RDY# (6) An active low status output indicating the ADC has no conversion ongoing and the SMD1108 can be accessed via the serial interface without risk of disturbing a conversion. GPO-0 to GPO-3 (28, 27, 26, 25) General purpose outputs that can be accessed via the two-wire serial interface. The register controlling these outputs is located in the GFS register section. The GPx outputs are open drain and will be active when a "1" is written to the corresponding bit position in GFS Register 0x98. The SMD1108 will power-up with the GPx bits cleared; therefore, the outputs will not be actively driven. AUTOMON (9) This input must be high to enable the Auto Monitor function. OV_IRQ# (13) This is an active low open drain output that is driven low when the selected over-voltage conditions are true. OC_IRQ# (12) This is an active low open drain output that is driven low when the selected over-current conditions are true. IRQ_RST# (7) The IRQ# outputs are latched. Strobing this signal low will reset the IRQ# outputs. They can also be cleared by accessing Register 99 (see Table 29). UV_OVRD (16) Forcing this input high will disable Under-Voltage reset conditions. FAULT_IRQ# (10) This is an active low open drain output that is driven low when the selected fault conditions are true.
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SMD1108
Preliminary
DEVICE OPERATION
THE ADC AND THE ANALOG SWITCH 10-bit ADC The 10-bit ADC is a self-clocking SAR implementation. In the manual mode of conversion the sample and hold operation will begin after the SMD1108 has received the request for conversion and the channel address. See Table 1. 8 Analog Channels The eight analog channels can be separated into two function blocks: the bottom four channels (VCC0/CH4 to VCC3/CH7) are primarily supply voltage monitors; the top four channels (CH0 to CH3) are primarily environmental monitors. All eight channels can be switched to the 10-bit ADC and have their inputs converted on-command. CH0 to CH3 may be placed in the Auto-Monitor mode. VCC0/CH4 to VCC3/CH7 provide four inputs to the analog switch that controls the analog inputs to the ADC converter. Although these channels cannot be placed in the Auto-Monitor mode, the host can request a direct conversion. Because these channels are designed to operate as supply voltage monitors they are each tied into a programmable comparator. The comparator threshold voltage is programmable and the polarity of the threshold is programmable. This allows very precise monitoring of underor over-voltage conditions. Paired with each of these
Signal to Noise ratio @ 25C. THD Peak harmonic intermodulation distortion 2nd order 3rd order DC Accuracy Resolution Minimum resolution for which no missing codes are guaranteed Relative accuracy DNL Positive full scale error VCC = 5V Unpolar offset error VCC = 2.7V to 3.6V VCC = 1.8V to 2.7V
2052 Table01
channels is an over-current input (OC0 to OC3) that is offset from its partner comparator by 50mV. TIMER FUNCTIONS WATCHDOG and LONGDOG The SMD1108 has two programmable Watchdog timers each with its own output (WDO# and LDO#) and a common reset input (WLDI). Both are independently programmable and both can be placed in an idle mode. See Register 8C. RST# This reset output is intended to be used to drive the backend logic. It is an active low open drain output that is driven low whenever VCC0, VCC1, VCC2 or VCC3 is below its programmed threshold and/or MR# is being driven low. It will stay low for the duration of the fault condition or the MR# low input and remain low for the duration of tPURST (the programmed reset pulse width) after removal of the fault condition or MR# returning high. It will also be driven low whenever an over-current condition is detected. See Register 8C. DLYD_RST# This output is activated by the same set of conditions as RST#. However, during a power-up operation it will not be immediately asserted. As soon as power to one of the VCC0/CH4 to VCC3/CH7 inputs is detected a time-out sequence will be started. The time-out period is programmable and should be equal to or greater than the worst case power-on skew between all the supplies being monitored. If all of the supplies have not reached their threshold before the time-out period, DLYD_RST# will be asserted. DLYD_RST# can then be used to disable a voltage sequencer such as the SMH4803A or SMH4804. See Register 8D. OUTPUTS FAULT and HEALTHY Two programmable outputs (active high or active low) that will respond to programmed source activators. See Registers 8F and 90 through 95. IRQs The interrupt outputs are active low open drain outputs that are driven low whenever one of the corresponding monitor inputs senses an excursion beyond its programmed value. See Registers 88, 89, and 98 through 9F.
7
70dB mon. -80dB min. -80dB min. -80dB min. 80s nom. 10 bits 10 bits 1/2LSB 1LSB 2LSB 2LSB
Conversion time @ 25 C.
Table 1. Typical ADC Performance
SUMMIT MICROELECTRONICS, Inc.
2052 2.0 10/05/01
SMD1108
Preliminary
SERIAL INTERFACE The SMD1108 has an industry standard 2-wire serial interface. It supports four (4) device-type addresses: 1010 for reading and writing the memory array; 1001 for reading and writing the nonvolatile limit registers and
tR tF tHIGH
initiating ADC conversions; 1011 for access to the configuration registers, and 0001 that is used for responses to the SMBALERT protocol In order to facilitate host system presence detection techniques the SMD1108 provides A0, A1 and A2 address inputs.
tLOW
SCL
tSU:SDA tHD:DAT tSU:DAT tSU:STO
tHD:SDA
tBUF
SDA In
tAA
tDH
SDA Out
2052 Fig01 1.0
Figure 1. Memory Timing
Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR Parameter SCL clock frequency Clock low period Clock high period Bus free time (1) Start condition setup time Start condition hold time Stop condition setup time Clock edge to valid output Data Out hold time (1) SCL and SDA rise time (1) SCL and SDA fall time (1) Data In setup time (1) Data In hold time (1) Noise filter SCL and SDA (1) Write cycle time Noise suppression 250 0 100 5 SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change Before new transmission Conditions Min. 0 4.7 4.0 4.7 4.7 4.0 4.7 0.3 0.3 1000 300 3.5 Max. 100 Units kHz s s s s s s s s ns ns ns ns ns ms
2052 Table02 1.0
Note (1) These values are guaranteed by design.
Table 2. Memory Timing
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2052 2.0 10/05/01 SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
MEMORY AND REGISTER OPERATION
The SMD1108 incorporates a memory that is configured as a 128 x 8 array. Concatenated with the memory array are the sixteen registers that hold the upper and lower limits for ADC comparison tables. Additional registers provide space for configuration usage. Another space is provided for individual channel conversion initiations and reading the conversion data. All Read and Write operations to memory are handled via an industry standard two-wire interface. The bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pullup resistor, located somewhere on the bus Input Data Protocol The protocol defines any device that sends data onto the bus as a transmitter and any device that receives data as a receiver. The device controlling data transmission is called the Master and the controlled device is called the Slave. In all cases the SMD1108 will be a Slave device since it never initiates any data transfers. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time, because changes on the data line while SCL is high will be interpreted as a Start or a Stop condition. START and STOP Conditions When both the data and clock lines are high the bus is said to be not busy. A high-to-low transition on the data line, while the clock is high, is defined as the Start condition. A low-to-high transition on the data line, while the clock is high, is defined as the Stop condition. Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the Master or the Slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line low to Acknowledge that it received the eight bits of data. The SMD1108 will respond with an Acknowledge after recognition of a Start condition and its Slave address byte. If both the device and a Write operation are selected, the SMD1108 will respond with an Acknowledge after the receipt of each subsequent 8-Bit word. In the Read mode the SMD1108 transmits eight bits of data, then releases the SDA line, and monitors the line for an Acknowledge signal. If an Acknowledge is detected, and no STOP condition is generated by the master, the SMD1108 will continue to transmit data. If the Master leaves the SDA line high (NACK) the SMD1108 will terminate further data transmissions and await a Stop condition before returning to the standby power mode. Device Addressing Following a start condition the Master must output the address of the Slave it is accessing. The most significant four bits of the Slave address are the device type identifier (DTI). For the SMD1108 the default memory DTI is 1010BIN. The next three bits in the serial data stream are the device's bus address. The bus address is assigned by biasing the A0, A1 and A2 pins into any one of eight unique addresses. The last bit of the data stream defines the operation to be performed: when set to 1 a Read operation is selected; when set to 0 a Write operation is selected. MEMORY WRITE OPERATIONS The SMD1108 allows two types of Write operations: byte Write and page Write. A byte Write operation writes a single byte during the nonvolatile write period (tWR). The page write operation allows up to 16 bytes in the same page to be written during tWR. Byte Write After the Slave address is sent (to identify the Slave device, and a Read or Write operation), a second byte is transmitted which contains the 8-Bit address of any one of the 128 words in the array. Upon receipt of the word address the SMD1108 responds with an Acknowledge. After receiving the next byte of data it again responds with an Acknowledge. The Master then terminates the transfer by generating a Stop condition, at which time the SMD1108 begins an internal write cycle. While the internal write cycle is in progress the SMD1108 inputs are disabled, and the device will not respond to any requests from the master. Page Write The SMD1108 is capable of a 16-byte page Write operation. It is initiated in the same manner as the byte Write operation, but instead of terminating the Write cycle after the first data word, the Master can transmit up to 15 more bytes of data. After the receipt of each byte the SMD1108 will respond with an Acknowledge.
SUMMIT MICROELECTRONICS, Inc.
2052 2.0 10/05/01
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SMD1108
Preliminary
The SMD1108 automatically increments the address for subsequent data words. After the receipt of each word the low order address bits are internally incremented by one. The high order bits of the address byte remain constant. Should the Master transmit more than 16 bytes, prior to generating the Stop condition, the address counter will rollover, and the previously written data will be overwritten. As with the byte Write operation all inputs are disabled during the internal write cycle. Refer to Figure 2 for the address, Acknowledge, and data transfer sequence. Acknowledge Polling When the SMD1108 is performing an internal Write operation it will ignore any new Start conditions. Since the device will only return an acknowledge after it accepts the Start, the part can be continuously queried until an acknowledge is issued, indicating that the internal Write cycle is complete. See the flow diagram (Figure 3) for the proper sequence of operations for polling. READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to 1. There are two different Read options: (1) Current Address Byte Read; or (2) Random Address Byte Read Current Address Read The SMD1108 contains an internal address counter which maintains the address of the last word accessed, increS T A R T AA A R 21 0 / W A C K S T A R T AA A R 21 0 / W A C K
Write Cycle In Progress
Issue Start Issue Stop Issue Slave Address and R/W = 0
ACK Returned Yes
No
Next Operation a Write? Yes Issue Address
No
Issue Stop
Proceed With Write
Await Next Command
2052 Fig03
Figure 3. Polling Sequence Typical Write Operation
AA A A A A A A 76 5 4 3 2 1 0 A C K DDDDDDDD 76543210 A C K DD 76 DD 10 A C K S T O P
Master SDA Slave
Typical Read Operation
A C K DDDDDDDD 76543210 DDDDDDDD 76543210 A C K DD 76 DD 10
Master SDA Slave
N A C K
S T O P
2052 Fig02 2.0
Figure 2. Address, Acknowledge and Data Transfer Sequence
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2052 2.0 10/05/01 SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
mented by one. If the last address accessed (either a Read or Write) was to address location n, the next Read operation would access data from address location n+1 and increment the current address pointer. When the SMD1108 receives the Slave address field with the R/W bit set to 1 it issues an acknowledge and transmits the 8Bit word stored at address location n+1. The current address byte Read operation only accesses a single byte of data. The Master issues a NACK and generates a Stop condition. At this point, the SMD1108 discontinues data transmission. Random Address Read Random address Read operations allow the Master to access any memory location in a random fashion. This operation involves a two-step process. First, the Master issues a Write command which includes the Start condition and the Slave address field (with the R/W bit set to Write) followed by the address of the word it is to read. This procedure sets the internal address counter of the SMD1108 to the desired address. After the word address Acknowledge is received by the master, the master immediately reissues a Start condition followed by another Slave address field with the R/W bit set to Read. The SMD1108 will respond with an Acknowledge and then transmit the 8 data bits stored at the addressed location. At this point, the Master issues a NACK and generates a Stop condition. The SMD1108 discontinues data transmission and reverts to its standby power mode. Sequential READ Sequential Reads can be initiated as either a current address Read or random access Read. The first word is transmitted as with the other byte Read modes (current address byte Read or random address byte Read). However, the Master now responds with an AcknowlSMBALERT
edge, indicating that it requires additional data from the SMD1108. The SMD1108 continues to output data for each Acknowledge received. The Master terminates the sequential Read operation with NACK and issues a Stop. During a sequential Read operation the internal address counter is automatically incremented with each Acknowledge signal. For Read operations all address bits are incremented, allowing the entire array to be read using a single Read command. After a count of the last memory address the address counter will rollover and the memory will continue to output data. SMBALERT The function of the SMBALERT output is similar to a standard interrupt. Whenever one of the selected channels exceeds its limits the SMBALERT pin will be driven low. This action begins an exchange of information across the 2-wire interface that establishes the source of the interrupt. As shown in Figure 4 the SMBALERT signal is driven low and the host responds with the Alert Response Address [0001 1001]. The SMD1108 will issue an Acknowledge and then output its address, starting with the device type identifier for the PSF registers [1001]. Following this the SMD1108 outputs its bus address reflecting the biasing of the A0, A1 and A2 pins. If the response to any bus address option is selected and the pins are not biased the read back will be [111]. The last bit is undefined. At this point the Host should not issue an ACK, but immediately generate a Stop condition. The SMD1108 will continue driving the SMBALERT output low until the Host responds back by generating a Start condition followed by the SMD1108 address. The SMD1108 will generate an ACK and release the SMBALERT pin.
SCL HOST
Alert Response Address 0001100R
S T O P
S T A R1 T
0
Device Address 01AA 21
A 0
X
SDA SMD1108
A C K 1 0 AAA 210 Device Address 0 1 X
2052 Fig04 1.0
A C K
Figure 4. SMBALERT Sequence
SUMMIT MICROELECTRONICS, Inc. 2052 2.0 10/05/01
11
SMD1108
Preliminary
REGISTERS
REGISTER READ/WRITE The registers are read and written using the same 2-wire bus as the memory. The Configuration Registers and the GFS Registers are written as shown in Figure 5. Reads of the registers must be executed like a random Read operation. That is, a dummy write must be issued in order to set the address pointer for the following Read.
A A AAA C Register Address C K 1 0 1 1 2 1 0 WK 80 thru 9F S T A R T Configuration Register Data A C K S T O P
Even though the ADC cannot be written, performing commanded conversions (non-auto-monitor mode) requires a dummy Write operation to select the proper channel and indicate the type of conversion process that is being requested. The sequence would be: address the device using 1001 as the DTI followed by the bus address and a write bit. The next byte contains the conversion process requested and the channel or channel group to be converted. Single Channel Conversion The single channel Read allows the host to perform manual conversions on a single channel. The state of bits CH2, CH1 and CH0 selects one-of-eight channels. Reading DTI 1001 will return the converted data. If the host continues clocking SCL without an interim Stop command the SMD1108 will continue conversions on the selected channel and output the data as clocked. See the timing sequence diagrams in Figure 7. Multi-Channel Conversion: 4 Command 001 will configure the channel conversion such that the MUX will switch channels 0 through 3 sequentially. Multi-Channel Conversion: 8 Command 011 will configure the channel conversion such that the MUX will switch channels 0 through 7 sequentially. Differential Conversion In order to provide a very accurate current sense the SMD1108 can perform a differential conversion on a selected CHx/OCx input combination. This is limited to channels 4 through 7 and their corresponding OC inputs. The measurement provides the differential voltage between the input channels (VCC0/CH4 to VCC3/CH7) and the over-current sense inputs (OC0 to OC3). The result is that differential noise is rejected and an accurate voltage drop across the sense resistor is measured.
2052 Fig05 1.0
Figure 5. Writing to the Configuration Registers The Limits Registers for channels 0 through 3 are located at the top of the ADC address space and utilize the 1001 DTI. Unlike the configuration registers that are limited to single byte Writes or Reads, the ADC limit registers can be written in page mode. The example In Figure 6 shows two byte Writes to configure the CH0 Lower Limit.
Register Address A A A F0: C AAA C DDC 1 0 0 1 2 1 0 WK 1 1 1 1 0 0 0 0 K x x x x x x 9 8 K S T A R T S T O P
Register Address A A A F1: CD D D DD D D D C AAA C 1 0 0 1 2 1 0 WK 1 1 1 1 0 0 0 1 K 7 6 5 4 3 2 1 0 K S T A R T S T O P
2052 Fig06 1.0
Figure 6. Writing to the Limits Registers
7 6 CMD 0 0 0 1 0 0 1 0 0 1 1 0 1 5 4 CH2 CH2 3 CH1 CH1 x x CH1 CH0 2 CH0 CH0 x x 1 0 Bit Function Single channel read mode Continuous read mode 1 Continuous read mode 2 Differential conversion
2052 Table03 1.0
Table 3. Command/Address Byte
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2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
S T A R T
1001
ACCCCCC C MMMHHH WK 2 1 0 2 1 0
CMD Bits Channel Address
A C K
S T O P
Dummy write sets the channel address
S T A R T
1001
A RC K
N A CCC A H H H DD CD D D D D D D D C 2 1 0 9 8 K7 6 5 4 3 2 1 0 K
Channel Address Echoed
S T O P
Read back of converted data includes the channel address that is being converted followed by the data.
optional ACK or NACK/STOP CCC A A H H H DD CD D D D D D D D C 9 8 K7 6 5 4 3 2 1 0 K 210 CCC A A H H H DD CD D D D D D D D C 9 8 K7 6 5 4 3 2 1 0 K 210
S T A R T
1001
A RC K
S T O P
In a continuous read mode the SMD1108 will clock data out as shown above repeating the channel address for each conversion that takes place. For the mult-channel conversions the channel numbers increment, e.g., n to n+1.
2052 Fig07 1.0
Figure 7. Continuous Read
M-ADD F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
MSB x D7 x D7 x D7 x D7 x D7 x D7 x D7 x D7 x D6 x D6 x D6 x D6 x D6 x D6 x D6 x D6 x D5 x D5 x D5 x D5 x D5 x D5 x D5 x D5 x D4 x D4 x D4 x D4 x D4 x D4 x D4 x D4 x D3 x D3 x D3 x D3 x D3 x D3 x D3 x D3 AR01 D2 AR02 D2 AR11 D2 AR12 D2 AR21 D2 AR22 D2 AR31 D2 AR32 D2 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1
LSB D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0
Function Channel #0 low limit Channel #0 low limit Channel #0 high limit Channel #0 high limit Channel #1 low limit Channel #1 low limit Channel #1 high limit Channel #1 high limit Channel #2 low limit Channel #2 low limit Channel #2 high limit Channel #2 high limit Channel #3 low limit Channel #3 low limit Channel #3 high limit Channel #3 high limit
2052 Table04
Note: ARxx is the Alert Region limit. See Environmental Automonitor Blocks description in the Applications Information section.
Table 4. ADC Registers Located at the Top of 1001 Address Space
SUMMIT MICROELECTRONICS, Inc.
2052 2.0 10/05/01
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SMD1108
Preliminary
REGISTER PARTITIONING The registers have been divided into two main functional blocks. The Configuration registers (from 0x80 through 0x95) are the primary setup registers that define the SMD1108 for its specific application. These registers can
Reg. # 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F Address configuration VREF configuration Timers 1 Timers 2 Quick trip Healthy/Fault configuration Healthy pin configuration Healthy pin configuration Fault pin configuration Fault pin configuration Fault mask Fault mask Reserved Reserved GPO register Software reset Status register Status register Reserved Reserved Fault latch Fault latch GFS Register
2052 Table05 1.0
be (1) left open for both Read and Write operations, (2) locked for Write but open for Read, or (3) totally blocked for both . The balance of the registers (the GSF registers) will frequently be used during system operation, so the lock combinations are more flexible. They can be (1) locked for Read and Writes, (2) open for Read and Write but excluding the configuration registers, (3) Read all registers but Write GSF only, or (4) Read and Write all registers. The organization, bit patterns and functions of the registers are illustrated in Tables 6 through 33. Registers 80 through 83 set the under-voltage threshold for the selected channel: CH4 through CH7. The register value is determined by subtracting 0.9V from the desired threshold, dividing the result by 0.02 and converting that to a hexadecimal value.
Reg. Name
Reg. Type
Channel configuration
Configuration Registers
The formula is (UVTH - 0.9) / 0.02 = Decimal value (convert to hexadecimal). For example, if the UV threshold is to be 4.6V: (4.6 - 0.9) / 0.02 = 185DEC = B9HEX
GFS Register
Table 5. Register Address Map
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2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
7 UV7
6 UV6
5 UV5
4 UV4
3 UV3
2 UV2
1 UV1
0 UV0
Function UV threshold voltage for VCC0/CH4
2052 Table06
Table 6. Register 80 VCC0/CH4 UV Threshold
7 UV7 6 UV6 5 UV5 4 UV4 3 UV3 2 UV2 1 UV1 0 UV0 Function UV threshold voltage for VCC1/CH5
2052 Table07
Table 7. Register 81 VCC1/CH5 UV Threshold
7 UV7 6 UV6 5 UV5 4 UV4 3 UV3 2 UV2 1 UV1 0 UV0 Function UV threshold voltage for VCC2/CH6
2052 Table08
Table 8. Register 82 VCC2/CH6 UV Threshold
7 UV7 6 UV6 5 UV5 4 UV4 3 UV3 2 UV2 1 UV1 0 UV0 Function UV threshold voltage for VCC3/CH7
2052 Table09
Table 9. Register 83 VCC3/CH7 UV Threshold
Registers 84 through 87 set the over-voltage threshold for the selected channel: CH4 through CH7. The OV threshold minimum is equal to 120% of the channel's UV threshold. An offset of as much as 244% of the UV threshold is possible.
7 x 6 x 5 x 4 OV4 3 OV3 2 OV2
The formula is [OVTH - (UVTH x 1.2)] / (UVTH x 0.04) = Decimal value (convert to hexadecimal). The maximum register value would be 31DEC = 1FHEX.
1 OV1
0 OV0
Function Over-voltage offset for VCC0/CH4
2052 Table10 1.0
Table 10. Register 84 VCC0/CH4 OV Threshold
7 x 6 x 5 x 4 OV4 3 OV3 2 OV2 1 OV1 0 OV0 Function Over-voltage offset for VCC1/CH5
2052 Table11 1.0
Table 11. Register 85 VCC1/CH5 OV Threshold
7 x
6 x
5 x
4 OV4
3 OV3
2 OV2
1 OV1
0 OV0
Function Over-voltage offset for VCC2/CH6
2052 Table12 1.0
Table 12. Register 86 VCC2/CH6 OV Threshold
7 x 6 x 5 x 4 OV4 3 OV3 2 OV2 1 OV1 0 OV0 Function Over-voltage offset for VC32/CH7
2052 Table13 1.0
Table 13. Register 87 VCC3/CH7 OV Threshold
SUMMIT MICROELECTRONICS, Inc. 2052 2.0 10/05/01
15
SMD1108
Preliminary
Registers 88 and 89 provide selective enabling of the channels and the channels' functions. When channels 0 through 3 are enabled any out-of-limit condition will activate the LIM_IRQ# and SMBALERT# outputs. Channels 4 through 7 are more complex in that they are inputs to three
instant action measurements: under-voltage, over-voltage and over-current. Each one of these measurements can be enabled on a channel by channel basis to activate one of the three potential output reactions.
7 x OV3 (CH7)
6 x OV2 (CH6)
5 x OV1 (CH5)
4 x OV0 (CH4)
3 UV3 (CH7) x
2 UV2 (CH6) x
1 UV1 (CH5) x
0 UV0 (CH4) x
Function A "1" enables the channel; an UV condition will cause a RESET. A "1" enables the channel; an OV condition will cause an OV_IRQ.
2052 Table14 1.0
Table 14. Register 88 Channel Enable -- Part 1
7 x
6 x
5 x
4 x
3 LIM3 (CH3)
2 LIM2 (CH2)
1 LIM1 (CH1)
0 LIM0 (CH0)
Function A "1" enables the channel; an out-oflimit condition will cause a LM_IRQ# and a SMBALERT. A "1" enables the channel; an overcurrent condition will cause an OC_IRQ#.
2052 Table15 1.1
OC3 (CH7)
OC2 (CH6)
OC1 (CH5)
OC0 (CH4)
x
x
x
x
Table 15. Register 89 Channel Enable -- Part 2 Register 8A controls access to the SMD1108 with regard to the 2-wire interface and the function blocks that are accessed through the 2-wire bus.
7 6 5 ACK 4 3 2 CE 0 1 x x x x x x x x x x 1 x x x x x x x x x x x x x 0 x x x x x x x x x x x x x Bits Function CE# input active low CE# input active high Responds to address pin biased address only Responds to any bus address EEPROM responds to 1010 EEPROM responds to 1110 ACK and access to DTI 1010 No ACK/ no access to DTI 1010 All registers locked: no read, no write Read and write GFS registers only (98 through 9F). All configuration registers locked. Read all registers. Wrilte GFS registers. Read and write all registers
2052 Table16 1.0
Reg. Access
Device Device Type Address x x 0 1 0 1 x x x x x x x x
x x x
0 1 0 0 1 1 0 1 0 1 x x x x
x x x x x x
Table 16. Register 8A Slave Address Configuration
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2052 2.0 10/05/01 SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
Register 8B controls the source for the ADC's reference, optional over-current trip values, and channel 3 vs. temp. sense enable.
7 6 5 4 3 TS 2 NVFL 1 OC x x x x x x x 0 1 0 1 0 0 0 0 1 1 0 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x 0 1 x x x x x x x x x x 0 VREF 0 1 x x x x x x x x x x x x Bits Function VREF = 2.048V VREF = 2.500V Over-current trip = 25mV Over-current trip = 50mV Disable non-volatile fault latch Enable non-volatile fault latch Disable temp sensor Enable temp sensor (vs. Channel 3) Reserved function. Set to 0. Reserved function. Set to 0. Use internally generated VREF Reserved Reserved Use VREF input
2052 Table17
VREF SOURCE
Reserved
Table 17. Register 8B Configuration
7 PRT1
6 PRT0
5 LD2
4 LD1
3 LD0
2 WD2 0 1
1 WD1 x 0 0 1 1 x x x x x x x x x
0 WD0 x 0 1 0 1 x x x x x x x x x
Bits Function Watch dog timer disabled 400ms Watch dog timer interval 800ms Watch dog timer interval 1600ms Watch dog timer interval 3200ms Watch dog timer interval Long dog timer disabled 800ms Long dog timer interval 1600ms Long dog timer interval 3200ms Long dog timer interval 6400ms Long dog timer interval 25ms Reset interval 50ms Reset interval 100ms Reset interval 200ms Reset interval
2052 Table18 2.0
x
x
x
1 1 1
x
x
0 1 1 1 1
x 0 0 1 1 x x x x
x 0 1 0 1 x x x x
x x x x x x x x x
0 0 1 1
0 1 0 1
x x x x
Table 18. Register 8C Reset Pulse Width and Timer Delays
SUMMIT MICROELECTRONICS, Inc. 2052 2.0 10/05/01
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SMD1108
Preliminary
Register 8D controls three delays. DRT2, DRT1, and DRT0 control the hold-off time period for generation of any IRQ output and define the hold-off for the DLYD_RST# output. OCD1 and OCD0 define the delay from the first
7 FWD1 6 FWD0 5 OCD1 4 OCD0 3 x 2 DRT2 0 1 x x x 0 0 1 1 0 0 1 1 0 1 0 1 x x x x 0 1 0 1 x x x x x x 1 1 1 x x x x x x x x
sensing of an over-current condition, and how long that condition exists before taking action. FWD1 and FWD0 control the hold-off period from the first sensing of a fault condition until recording all active conditions.
1 DRT1 x 0 0 1 1 x x x x x x x x 0 DRT0 x 0 1 0 1 x x x x x x x x Bits Function Delayed reset timer disabled 200ms Delayed reset timer interval 400ms Delayed reset timer interval 800ms Delayed reset timer interval 1600ms Delayed reset timer interval 25s Over-current trip delay 50s Over-current trip delay 100s Over-current trip delay 200s Over-current trip delay Fault write sense delay off 50s Fault write sense delay 100s Fault write sense delay 200s Fault write sense delay
2052 Table19 1.0
Table 19. Register 8D Reset Pulse Width and Timer Delays
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2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
Register 8E selects the Quick Trip thresholds. The thresholds are interrelated with the value of the internal VREF controlled by the state of bit 1 in Register 8B.
7 QT1 CH4 6 QT0 CH4 5 QT1 CH5 4 QT0 CH5 3 QT1 CH6 2 QT0 CH6 1 QT1 CH7 0 x x x x x x 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 x x x x 0 1 0 1 x x x x x x x x x x x x 0 1 0 1 x x x x x x x x x x x x x x x x x x x x 0 QT0 CH7 0 1 0 1 x x x x x x x x x x x x Off 50mV/75mV 75mV/100mV 125mV/150mV Off 50mV/75mV 75mV/100mV 125mV/150mV Off 50mV/75mV 75mV/100mV 125mV/150mV Off 50mV/75mV 75mV/100mV 125mV/150mV
2052 Table20 1.0
Bits Function: QT threshold
Table 20. Register 8E Quick Trip Thresholds
SUMMIT MICROELECTRONICS, Inc.
2052 2.0 10/05/01
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SMD1108
Preliminary
Register 8F controls the function of the HEALTHY# and FAULT# outputs and the conditions that can drive them. All latched HEALTHY# or FAULT# conditions are cleared by IRQ_RST#
7
6
5
Fault# Reset
4
Fault# Latch
3
Fault# State
2
Healthy# Reset
1
Healthy# Latch
0
Healthy# State
Bits Function HEALTHY# output active low HEALTHY# outputactive high Do not latch HEALTHY# Latch HEALTHY# HEALTHY# unaffected by reset HEALTHY# goes false on reset FAULT# output active low FAULT# output active high Do not latch FAULT# Latch FAULT# FAULT# unaffected by reset FAULT# goes true on reset UV_OVRD# will override FAULT# conditions HEALTHY# & FAULT# ignore UV_OVRD# Enabled channels affect HEALTHY# & FAULT# Disabled channels affect HEALTHY# & FAULT#
2052 Table21
Healthy# UV_OVRD# & Fault#
x x x x x x x 0 1 0 1 0 1 0 1 x x x x x x x x x x x x 0 1 x x x x x x x x 0 1 x x x x x x x x x x 0 1 x x x x x x x x x x x x
0 1 x x x x x x x x x x x x x x
Table 21. Register 8F HEALTHY# and FAULT# Output Control
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2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
Registers 90 through 93 control the sources of activation for the HEALTHY# and FAULT# outputs. For the HEALTHY# output to be true all the selected sources must be within their limits. This is effectively an ANDing
function. For the FAULT# output to be true only one of the selected sources need be out of limits (ORing). If the same sources for HEALTHY# and FAULT# are selected then only one of the two outputs can be true at one time.
7 OV3 CH7 0 1
6 OV2 CH6 0 1
5 OV1 CH5 0 1
4 OV0 CH4 0 1
3 UV3 CH7 0 1
2 UV2 CH6 0 1
1 UV1 CH5 0 1
0 UV0 CH4 0 1
Bit Function HEALTHY# signal unaffected by condition HEALTHY# signal goes false on condition
2052 Table22
Table 22. Register 90 HEALTHY# Deactivation Sources
7 OC3 CH7 0 1
6 OC2 CH6 0 1
5 OC1 CH5 0 1
4 OC0 CH4 0 1
3 LIM3 CH3 0 1
2 LIM2 CH2 0 1
1 LIM1 CH1 0 1
0 LIM0 CH0 0 1
Bit Function HEALTHY# signal unaffected by condition HEALTHY# signal goes false on condition
2052 Table23
Table 23. Register 91 HEALTHY# Deactivation Sources
7 OV3 CH7 0 1
6 OV2 CH6 0 1
5 OV1 CH5 0 1
4 OV0 CH4 0 1
3 UV3 CH7 0 1
2 UV2 CH6 0 1
1 UV1 CH5 0 1
0 UV0 CH4 0 1
Bit Function FAULT# signal unaffected by condition FAULT# signal goes true on condition
2052 Table24
Table 24. Register 92 FAULT# Activation Sources
7 OC3 CH7 0 1
6 OC2 CH6 0 1
5 OC1 CH5 0 1
4 OC0 CH4 0 1
3 LIM3 CH3 0 1
2 LIM2 CH2 0 1
1 LIM1 CH1 0 1
0 LIM0 CH0 0 1
Bit Function FAULT# signal unaffected by condition FAULT# signal goes false on condition
2052 Table25
Table 25. Register 93 FAULT# Activation Sources
SUMMIT MICROELECTRONICS, Inc.
2052 2.0 10/05/01
21
SMD1108
Preliminary
Registers 94 & 95 are similar to FAULT# registers 92 and 93. If any one of the selected sources is true the fault condition will be recorded in the nonvolatile fault latches 9E and 9F. This in turn will drive the FLT_IRQ# output low.
7 OV3 CH7 0 1 6 OV2 CH6 0 1 5 OV1 CH5 0 1 4 OV0 CH4 0 1 3 UV3 CH7 0 1 2 UV2 CH6 0 1 1 UV1 CH5 0 1 0 UV0 CH4 0 1 Bit Function FAULT# latch unaffected by condition FAULT# latch records out of limit condition
2052 Table26
Table 26. Register 94 FAULT# Latch Mask
7 OC3 CH7 0 1
6 OC2 CH6 0 1
5 OC1 CH5 0 1
4 OC0 CH4 0 1
3 LIM3 CH3 0 1
2 LIM2 CH2 0 1
1 LIM1 CH1 0 1
0 LIM0 CH0 0 1
Bit Function FAULT# latch unaffected by condition FAULT# latch records out of limit condition
2052 Table27
Table 27. Register 95 FAULT# Latch Mask
THE GFS REGISTERS The balance of the registers can be thought of as the operation registers. That is, the previous registers define 7 6 5 4 3 GPO3 x x x x 0 1 2 GPO2 0 1
the part's function and their contents will most likely be written once and never altered. The following GPO, fault, and status registers will be actively read and written during system operation. 1 GPO1 0 1 0 GPO0 0 1 Bit Function Power on state -- non-active Corresponding output to ground
2052 Table28 1.0
Table 28. GFS Register 98 GPO Output Control Register 99 provides a software method for activating a RESET output or clearing an IRQ (this effectively mimics the IRQ_RST# input).
7
6
5
4
3
2
1 Soft Reset
0 Clear IRQ 1 x
Bit Function Clears any IRQ except FLT_IRQ# Starts reset cycle, then self clears
2052 Table29 1.0
Reserved 0 0 0 0 0 0
x 1
Table 29. GFS Register 99 GPO Output Control
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2052 2.0 10/05/01 SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
Registers 9A and 9B are the status registers. These registers are read-only and are volatile. The Status Register is cleared by forcing the IRQ_RST# input low.
7 OV3 CH7 0 1
6 OV2 CH6 0 1
5 OV1 CH5 0 1
4 OV0 CH4 0 1
3 UV3 CH7 0 1
2 UV2 CH6 0 1
1 UV1 CH5 0 1
0 UV0 CH4 0 1
Bit Function Condition not the cause of an IRQ Condition the cause of an IRQ
2052 Table30 1.0
Table 30. GFS Register 9A Status Register (Read Only)
7 OC3 CH7 0 1
6 OC2 CH6 0 1
5 OC1 CH5 0 1
4 OC0 CH4 0 1
3 LIM3 CH3 0 1
2 LIM2 CH2 0 1
1 LIM1 CH1 0 1
0 LIM0 CH0 0 1
Bit Function Condition not the cause of an IRQ Condition the cause of an IRQ
2052 Table31 1.0
Table 31. GFS Register 9B Status Register (Read Only)
Registers 9E and 9F are the Fault registers. These registers are nonvolatile and can only be cleared by writing to the affected bit. This register is cleared by writing a 0 to the affected bit location.
7 OV3 CH7 0 1 6 OV2 CH6 0 1 5 OV1 CH5 0 1 4 OV0 CH4 0 1 3 UV3 CH7 0 1 2 UV2 CH6 0 1 1 UV1 CH5 0 1 0 UV0 CH4 0 1 Bit Function Condition not the cause of an IRQ Condition the cause of an IRQ
2052 Table32 1.0
Table 32. GFS Register 9E NV Fault Latch
7 OC3 CH7 0 1
6 OC2 CH6 0 1
5 OC1 CH5 0 1
4 OC0 CH4 0 1
3 LIM3 CH3 0 1
2 LIM2 CH2 0 1
1 LIM1 CH1 0 1
0 LIM0 CH0 0 1
Bit Function Condition not the cause of an IRQ Condition the cause of an IRQ
2052 Table33 1.0
Table 33. GFS Register 9F NV Fault Latch
SUMMIT MICROELECTRONICS, Inc. 2052 2.0 10/05/01
23
SMD1108
Preliminary
APPLICATIONS INFORMATION
Overview The SMD1108 Auto-Monitor ADC is designed to monitor the environmental parameters on a telecommunications line card or subsystem. Figure 9 shows the SMD1108 monitoring four dedicated supply lines -- in this example: 5V, 3.3V 2.5V, and 1.8V -- coming in Connector J16. For each of these 4 channels there is an associated undervoltage, over-voltage and over-current detection circuit. These voltage and current inputs are connected internally to an `Instant Action block' (Figure 8), and, in the event of a failure, can be programmed to log the fault in an internal nonvolatile memory. The ability to log faults directly into a nonvolatile status register allows systems designers the ability to record data relating to system performance, so that data about the environment is logged immediately in the event of a failure on the subsystem. This provides the ability to fault record -- which can be critical when trying to diagnose system faults -- during reliability tests or field failures. The SMD1108 also allows data to be downloaded while still mounted on the line card. The SMD1108 provides out-of-limit monitoring via four environmental automonitor inputs (CH0 to CH3). Absolute measurement of the parameters via an ADC allows engineers to monitor the long term performance of the subsystem to predict system failure allowing scheduled maintenance to repair the problem before the failure occurs. For example, a current increasing over a period of months on an optical interface where a laser is aging, or the DC output of a DC-DC Converter. There are four general-purpose open collector outputs which can be
Current Flow
used to drive low current signals such as status LEDs. They are all controlled via the serial data bus. Summit's Windows-based Graphical User Interface (GUI) Programming Software will allow the engineer to program the SMD1108 via a host PC running Windows 9x, 2000 or NT. The GUI is also available on the website at www.summitmicro.com. Power Supplies The SMD1108 is designed to take power via the inputs VCC0/Ch4 through VCC3/Ch7. These 4 inputs are internally diode-ORed. Consequently the highest supply voltage actually supplies the current to the device. At least one of these supplies must be above 2.7V for correct device operation. Summit recommends 100nF decoupling capacitors across all voltage supply inputs. For more information on these inputs see Figure 8, the Instant Action Block. The AUXVCC signal is provided to create a backup supply. This pin should have a 10F capacitor to ground, and should be isolated from the main supply. AUXVCC is also used to power the part to access the nonvolatile memory without having power applied to the rest of the board. See recommended connections in the Serial Interface section. 8 Channel 10 bit ADC The SMD1108 can monitor system parameters and measure each value to an absolute level. The analog acquisition system consists of an 8-to-1 MUX, a 10-bit ADC, voltage references, and the automonitor logic. The ADC's inputs are grouped into two banks of four. The CH0 to CH3 inputs are the primary environmental automonitor channels, and the VCC0/Ch4 to VCC3/Ch7 inputs are the supply monitors (see Figure 8). The interface to the ADC is made via the two-wire serial data port. When the SMD1108 is in automonitor mode (signal AUTOMON high) the serial interface is disabled to prevent any noise from the serial bus disturbing the ADC conversion. During the development process the engineer can read the values of the ADC channels directly using the Windows GUI. The RDY# signal indicates when the ADC is busy in conversion. There are three sources for the reference voltage on the ADC. Two voltages are generated internally: 2.5V and 2.048V. These are doubled internally and generate full scale values of 5V and 4.096V (or 4mV/bit), respectively. In addition, it is possible to source the reference voltage externally. These three options are programmable through the GUI software.
CHn
RSENSE
OCn
Programmed OC Thresholds 25mV, 50mV
OC Signal
Programmed QuickTripTM Thresholds 50mV, 75mV, 125mV
QuickTripTM
Programmed UV Threshold 0.9V to 6.0V Programmed OV Offset +120%/-244%
UV Signal
OV Signal
2052 Fig08
Figure 8. Instant Action Block
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2052 2.0 10/05/01 SUMMIT MICROELECTRONICS, Inc.
J9 3 2 1 SCL SDA MR#
2 4 6 8 10 1 3 5 7 9
5V J8 GND GND 5V R19 10k R18 10k SW1 SW2 J7 J4 R13 50k R25 50k J1 I2C
R29 10k
R32 10k
R33 10k
R4 0.005
R3 0.005
R2 0.005
R1 0.005
3 2 1
SMD1108
Preliminary
2052 Fig09
C11 0.1F J2 J3
3 2 1
SUMMIT MICROELECTRONICS, Inc.
R20 10k R17 1k ENVIRONMENTAL SENSORS J6 J13 J14 R16 1k
5V
J12
R30 10k
5V
46 47 45 44 43 22 7 5
RT1 t
R34 10k
D1 D2 R6 1k
R5 1k
SDA SCL A2 A1 A0 CE#
IRQ_RST# MR#
R35 10k C14 2.2F C13 2.2F C12 2.2F C2 0.1F C4 0.1F C3 0.1F
C15 2.2F
C5 0.1F
33 32 31 30 CH0 CH1 CH2 CH3
D3 D4 28 27 26 25 GPO-0 GPO-1 GPO-2 GPO-3 R8 1k
R7 1k
R31 10k
D5 D6 R10 1k
R9 1k
J16 Female
Figure 9. Typical Application Schematic
SMD1108
41 40 39 38 VCC0/CH4 VCC1/CH5 VCC2/CH6 VCC3/CH7
2052 2.0 10/05/01
FAULT_IRQ# RDY# OV_IRQ# OC_IRQ# DLYD_RST# LIM_IRQ# SMBALERT RST# HEALTHY# FAULT#
34 35 36 37 OC3 OC2 OC1 OC0
D9 D10 R1 1k
GNDA 1.8V 2.5V 3.3V 5.0V GNDB
1 2 3 4 5 6 7 8
10 6 13 12 14 11 4 15 23 24
R2 1k
D12 R22 1k D13
R21 1k
C7 C6 C9 C8 0.1F 0.1F 0.1F 0.1F
J17 Male
D14
R23 1k
WD_EN# UV_OVRD AUTOMON WLDI 3 16 9 48
LDO# WDO# VREFOUT VREFIN AUXVCC
8 GND 17 PGND 18 DGND 19 AGND
D15
R24 1k
1 2 20 29 42
GNDB 5.0V 3.3V 2.5V 1.8V GNDA
8 7 6 5 4 3 2 1
D7 D8 5V R12 1k
R11 1k
R36 10k 123
R26 10k 123
R27 10k 123
R28 10k 123
R38 D17 1k C1 10F C10 0.1F J10 J11 J5 R37 D16 1k
J15
25
SMD1108
Preliminary
Temperature Sensor The internal temperature sensor can be accessed as a multiplexed optional input on CH3. Channel 3 can be set to read an internal temperature dependant device with a range of 128C. The 10-bit ADC converts the temperature reading to data in 2's complement format, and is accurate to 1/4C. The GUI software can enable the Temperature Sensor and will change the displayed reading on CH3 from volts to C. Instant Action Block A single channel of the Instant Action Block is shown in Figure 8. The SMD1108 has a block of 12 nonvolatile threshold comparators dedicated to monitoring the status of the supply lines, they are arranged as: Four Over-Voltage comparators, Four Under-Voltage comparators, and Four Over-Current comparators. This structure has been adopted to ensure all supplies are continuously monitored, because if a supply interruption occurred while the ADC was sampling another channel the interruption could be missed. Each channel can set the UV threshold anywhere in the range from 0.9V to 6V in 20mV steps. OV thresholds are offset from the UV threshold, and the value to be entered into the register can be calculated from:
OVTH (UVTH x 1.2) UVTH x 0.04
Sense resistors Care should be taken when designing the PCB layout for the Sense resistors. A Kelvin, or 4 Wire, connection scheme should be adopted as shown in Figure 10. Circuit accuracy can be affected if the PCB trace to the resistor is not optimized. Voltage drops across copper traces due to current flow can cause additional errors.
High Current Path
Kelvin Sense Traces
Sense Resistor
2052 Fig10
Figure 10. Kelvin-connected Sense Resistor Each of the alarm signals can be used to change the status of the following outputs: HEALTHY#, FAULT#, FAULT_IRQ#, RST#, OV_IRQ#, and OC_IRQ# Environmental Automonitor Blocks The 4 environmental channels, Channels 0 through 3, are monitored autonomously by the internal logic of the SMD1108 when it is in Automonitor mode and the individual channels have been enabled. The ADC continuous samples the input and compares the value against two pre-programmed values held in a nonvolatile store.
Solid line indicates alert set if conv = limit Dashed line indicates alert NOT set if conv = limit 3FF ALERT REGION ALERT REGION 3FF
.
When the UV threshold is enabled it is internally ORed to the RST# signal. Please note if UV Override (UV_OVRD) is active then these thresholds are ignored. UV Override is provided to allow voltage margining during production `burning in' of the line cards; this prevents Alarm signals from being generated during this test. The over-current comparator is offset from the input voltage by a programmable threshold, which can be set to 50, 75 or 150mV. Selection of the sense resistor is made using Ohms Law, for example: Offset Voltage / Max Current = R sense If a Two Amp limit using the 150mV threshold is specified, it would require a resistance of 75m.
ALERT REGION 000
"00"
ALERT REGION 000
"01"
3FF Upper limit Lower limit ALERT REGION ALERT REGION
Monitor Option Bits 3FF x x Lower Upper
000
"10" "11"
000
2052 Fig11
Figure 11. Alert Threshold Settings
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2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
Each Channel has two 10-bit threshold registers, one for the high threshold and one for the low threshold. The channels can be set up to measure the signals as shown in Figure 11. If the ADC output falls into the Alert region the SMD1108 can be programmed to change any of the following signals: HEALTHY#, FAULT#, FAULT_IRQ#, and LIM_IRQ#. In addition, the SMB Alert Output will become active. SMBALERT is a special interrupt which can be used to signal to the processor that a fault has occurred. The processor will issue a special SMB message on the serial data bus, all devices on the serial data bus will listen to the command, and the device responsible for the SMB Alert will identify its own address, as defined by the address pins (see serial data bus section). Note the processor must take the SMD1108 out of Automonitor mode prior to sending the SMB message. General Purpose Outputs There are 4 General Purpose Outputs which can be controlled via the serial data bus. Each signal can be controlled independently. These are open collector outputs, which are capable of sinking 5mA, suitable for driving low current LEDs. The Serial Data Bus must be active in order to control the GPO's (i.e., not in Automonitor mode). Nonvolatile Memory In addition to programming registers the SMD1108 contains 1k bits of NV Memory, which can be accessed by a host processor using the Serial Data Bus. The NV memory looks like a conventional Serial EEPROM, using Serial Data Bus address 1010. The memory is organized as 128 x 8 bits. Processor Supervisor Functions Integrated into the SMD1108 are the typical functions found around a host microprocessor/microcontroller. These include reset controller, manual reset function, and
a two stage watchdog timer. The RST# output signal is a function of the following inputs: Voltage Thresholds in CH4 through CH7 (can be overridden by UV_OVRD signal), the Manual Reset Input (MR#), and an Alarm from the Instant Action Block. For each channel, which has an active UV Threshold, all channels must have a voltage above their pre-programmed UV threshold. The MR# input is intended for a front panel reset switch. This input is debounced internally and will produce a rest pulse width according to the values programmed in using the GUI. A two-stage timer is provided: the Watchdog and Longdog timers. Each timer has its own respective output (WDO and LDO), but both are triggered from a common input signal (WLDI). Normally the shorter time is programmed in the Watchdog timer. The Watchdog timer and Longdog Timer values are set in the GUI. Serial Data Bus Interface The SMD1108 has a serial data bus interface using clock (SCL) and data (SDA) lines. See the Serial Interface section for timing requirements. There are also three Address pins -- A2, A1, A0 -- which are used to select the device bus address. This allows 8 unique addresses on the bus. If the address range needs further expansion a separate CE# pin is provided. As the CE# pin enables all data bus communication with the device it must be set to the correct level for access. The first 4 bits of the 8 bit data sent to the SMD1108 are used to access various internal functions: 0001BIN -- SMB Alert Protocol, 1001BIN -- Limit Register Access (CH0 to CH3), 1010BIN -- Memory Access, 1011BIN -- Configuration Register Access.
SUMMIT MICROELECTRONICS, Inc.
2052 2.0 10/05/01
27
SMD1108
Preliminary
PACKAGE
48 PIN TQFP PACKAGE
[A] 0.354 BSC (9.00) [B] 0.276 BSC (7.00)
Ref. JEDEC MS-026
0.02 BSC (0.5)
Inches (Millimeters)
0.007 - 0.011 (0.17 - 0.27)
DETAIL "A"
[A] [B] 0.037 - 0.041 (0.95 - 1.05) 0.039 (1.00)
Pin 1
0.047 MAX (1.2)
0.004 - 0.008 (0.09 - 0.20)
0.018 - 0.030 (0.45 - 0.75)
A
B
DETAIL "B"
48 Pin TQFP
ORDERING INFORMATION
SMD1108 Base Part Number
F Package F = TQFP
2052 Tree 1.0
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2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.
SMD1108
Preliminary
PART MARKING
SUMMIT
.
SMD1108 F
L YY WW
F = Package type (TQFP)
L = Lot number YY = Year WW = Work Week
NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. This document supersedes all previous versions. Power Management for CommunicationsTM (c) Copyright 2001 SUMMIT Microelectronics, Inc.
I2C is a trademark of Philips Corporation.
SUMMIT MICROELECTRONICS, Inc. 2052 2.0 10/05/01
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